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(R)
X5163, X5165
Data Sheet May 16, 2005 FN8128.1
CPU Supervisor with 16Kbit SPI EEPROM Description
These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
Features
* Selectable watchdog timer * Low VCC detection and reset assertion - Five standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V * Determine watchdog or low voltage reset with a volatile flag bit * Long battery life with low power consumption - <50A max standby current, watchdog on - <1A max standby current, watchdog off - <400A max active current during read * 16Kbits of EEPROM * Built-in inadvertent write protection - Power-up/power-down protection circuitry - Protect 0, 1/4, 1/2 or all of EEPROM array with Block LockTM protection - In circuit programmable ROM mode * 2MHz SPI interface modes (0,0 & 1,1) * Minimize EEPROM programming time - 32-byte page write mode - Self-timed write cycle - 5ms write cycle time (typical) * 2.7V to 5.5V and 4.5V to 5.5V power supply operation * Available packages - 14-lead TSSOP, 8-lead SOIC
Pinouts
8-LEAD SOIC/PDIP X5163, X5165 CS/WDI SO WP VSS 1 2 3 4 X5163, X5165 8 7 6 5 VCC RESET/RESET SCK SI 14-LEAD TSSOP X5163, X5165 CS/WDI SO NC NC NC WP VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RESET/RESET NC NC NC SCK SI
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X5163, X5165 Block Diagram
Watchdog Transition Detector WP SI SO SCK CS/WDI Data Register Command Decode & Control Logic VCC Threshold Reset Logic Protect Logic RESET/RESET Status Register EEPROM Array 4K Bits 4K Bits 8K Bits Reset & Watchdog Timebase X5163 = RESET X5165 = RESET Watchdog Timer Reset
VCC VTRIP
+ -
Power-on and Low Voltage Reset Generation
Pin Description
PIN (SOIC/PDIP) 1 PIN TSSOP 1 NAME CS/WDI FUNCTION Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting of the Watchdog Timer control and the memory write protect bits. Ground Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/ RESET goes active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge of CS will reset the Watchdog Timer. RESET/RESET goes active on power-up at 1V and remains active for 200ms after the power supply stabilizes. Supply Voltage No internal connections
2 3 4 5
2 6 7 8
SO WP VSS SI
6
9
SCK
7
13
RESET/ RESET
8
14 3-5,10-12
VCC NC
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X5163, X5165 Principles Of Operation
Power-on Reset
Application of power to the X516, /X5165 activates a Poweron Reset Circuit. This circuit goes active at 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. To set the new VTRIP voltage, apply the desired VTRIP threshold to the VCC pin and tie the CS/WDI pin and the WP pin HIGH. RESET and SO pins are left unconnected. Then apply the programming voltage VP to both SCK and SI and pulse CS/WDI LOW then HIGH. Remove VP and the sequence is complete.
CS VP SCK VP SI
Low Voltage Monitoring
During operation, the X5163, X5165 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms.
FIGURE 1. SET VTRIP VOLTAGE
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent a RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be "locked" by tying the WP pin LOW and setting the WPEN bit HIGH.
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, AND THE SCK pin HIGH. RESET and SO pins are left unconnected. Then apply the programming voltage VP to the SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove VP and the sequence is complete.
VCC Threshold Reset Procedure
The X5163, X5165 has a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or for higher precision in the VTRIP value, the X5163, X5165 threshold may be adjusted.
CS VCC
SCK
VP SI
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure directly makes the change. If the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value.
FIGURE 2. RESET VTRIP VOLTAGE
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VTRIP PROGRAMMING
EXECUTE RESET VTRIP SEQUENCE
SET VCC = VCC APPLIED = DESIRED VTRIP
NEW VCC APPLIED = OLD VCC APPLIED + ERROR
EXECUTE SET VTRIP SEQUENCE
NEW VCC APPLIED = OLD VCC APPLIED - ERROR
APPLY 5V TO VCC
EXECUTE RESET VTRIP SEQUENCE
DECREMENT VCC (VCC = VCC - 50MV)
NO
RESET PIN GOES ACTIVE?
YES
ERROR > -EMAX
MEASURED VTRIP - DESIRED VTRIP
ERROR > EMAX
ERROR < EMAX
EMAX = MAXIMUM DESIRED ERROR
DONE
FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART
VP 4.7K X5163, X5165 1 NC VTRIP ADJ. PROGRAM + 2 3 4 8 7 6 5 NC 4.7K RESET NC
10K
10K
RESET VTRIP TEST VTRIP SET VTRIP
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
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X5163, X5165 SPI Serial Memory
The memory portion of the device is a CMOS Serial EEPROM array with Intersil's block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. It contains an 8-bit instruction register that is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off.
Write Enable Latch
The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 7). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status Register. The Status Register may be read at any time, even during a Write Cycle. The Status Register is formatted as follows:
7 WPEN 6 FLB 5 WD1 4 WD0 3 BL1 2 BL0 1 WEL 0 WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a "1", a nonvolatile write operation is in progress. When set to a "0", no write is in progress.
TABLE 1. INSTRUCTION SET INSTRUCTION NAME WREN SFLB WRDI/RFLB RSDR WRSR READ WRITE INSTRUCTION FORMAT* 0000 0110 0000 0000 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 OPERATION Set the Write Enable Latch (Enable Write Operations) Set Flag Bit Reset the Write Enable Latch/Reset Flag Bit Read Status Register Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits) Read Data from Memory Array Beginning at Selected Address Write Data to Memory Array Beginning at Selected Address
NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. TABLE 2. BLOCK PROTECT MATRIX WREN CMD WEL 0 1 1 1 STATUS REGISTER WPEN X 1 0 X DEVICE PIN WP# X 0 X 1 BLOCK PROTECTED BLOCK Protected Protected Protected Protected BLOCK UNPROTECTED BLOCK Protected Writable Writable Writable STATUS REGISTER WPEN, BL0, BL1, WD0, WD1 Protected Protected Writable Writable
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The Write Enable Latch (WEL) bit indicates the Status of the Write Enable Latch. When WEL = 1, the latch is set HIGH and when WEL = 0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction. The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory.
STATUS REGISTER BITS BL1 0 0 1 1 BL0 0 1 0 1 STATUS REGISTER BITS WD1 1 1 WD0 0 1 WATCHDOG TIME OUT (TYPICAL) 200 milliseconds disabled
The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The Flag bit is automatically reset upon powerup. This flag can be used by the system to determine whether a reset occurs as a result of a watchdog time out or power failure. The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide an In-Circuit Programmable ROM function (Table 2). WP is LOW and WPEN bit programmed HIGH disables all Status Register Write Operations.
ARRAY ADDRESSES PROTECTED X516X None $0600-$07FF $0400-$07FF $0000-$07FF
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog bits from inadvertent corruption. In the locked state (Programmable ROM Mode) the WP pin is LOW and the nonvolatile bit WPEN is "1". This mode disables nonvolatile writes to the device's Status Register. Setting the WP pin LOW while WPEN is a "1" while an internal write cycle to the Status Register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the Status Register.
The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time Out Period. These nonvolatile bits are programmed with the WRSR instruction.
STATUS REGISTER BITS WD1 0 0 WD0 0 1 WATCHDOG TIME OUT (TYPICAL) 1.4 seconds 600 milliseconds
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
INSTRUCTION SI 15 14
16 BIT ADDRESS 13 3 2 1 0
DATA OUT HIGH IMPEDANCE SO 7 MSB 6 5 4 3 2 1 0
FIGURE 5. READ EEPROM ARRAY SEQUENCE
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When WP is HIGH, all functions, including nonvolatile writes to the Status Register operate normally. Setting the WPEN bit in the Status Register to "0" blocks the WP pin function, allowing writes to the Status Register when WP is HIGH or LOW. Setting the WPEN bit to "1" while the WP pin is LOW activates the Programmable ROM mode, thus requiring a change in the WP pin prior to subsequent Status Register changes. This allows manufacturing to install the device in a system with WP pin grounded and still be able to program the Status Register. Manufacturing can then load Configuration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the block lock bits, and finally set the "OTP mode" by setting the WPEN bit. Data changes now require a hardware change. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be "0's". The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. For the Page Write Operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 8). To write to the Status Register, the WRSR instruction is followed by the data to be written (Figure 9). Data bits 0 and 1 must be "0". While the write is in progress following a Status Register or EEPROM Sequence, the Status Register may be read to check the WIP bit. During this time the WIP bit will be high.
Read Sequence
When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence (Figure 5). To read the Status Register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the Status Register are shifted out on the SO line. Refer to the Read Status Register Sequence (Figure 6).
Operational Notes
The device powers-up in the following state: * The device is in the low power standby state. * A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. * SO pin is high impedance. * The Write Enable Latch is reset. * The Flag Bit is reset. * Reset Signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent inadvertent writes: * A WREN instruction must be issued to set the Write Enable Latch. * CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.
Write Sequence
Prior to any attempt to write data into the device, the "Write Enable" Latch (WEL) must first be set by issuing the WREN instruction (Figure 7). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the Write Operation without taking CS HIGH after issuing the WREN instruction, the Write Operation will be ignored.
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CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
INSTRUCTION SI
DATA OUT SO HIGH IMPEDANCE 7 MSB 6 5 4 3 2 1 0
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS
0 SCK
1
2
3
4
5
6
7
SI
SO
HIGH IMPEDANCE
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
INSTRUCTION SI 15 14
16 BIT ADDRESS 13 3 2 1 0 7 6 5
DATA BYTE 1 4 3 2 1 0
CS 32 SCK 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2 SI 7 6 5 4 3 2 1 0 7 6
DATA BYTE 3 5 4 3 2 1 0 6 5
DATA BYTE N 4 3 2 1 0
FIGURE 8. WRITE SEQUENCE
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CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION SI 7 6 5 4
DATA BYTE 3 2 1 0
SO
HIGH IMPEDANCE
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
Symbol Table
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM LO TO W HIGH MAY CHANGE FROM HIGH TO LOW DON'T CARE: CHANGES ALLO ED W N/A OUTPUTS WILL BE STEADY WILL CHANGE FROM LO TO W HIGH WILL CHANGE FROM HIGH TO LOW CHANGING: STATE NOT KNO WN CENTER LINE IS HIGH IMPEDANCE
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Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . .-65 to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150C Voltage on any pin with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +7V D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300C
Recommended Operating Conditions
Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Specifications Over operating conditions unless otherwise specified.
LIMITS SYMBOL ICC1 ICC2 ISB1 ISB2 ISB3 ILI ILO VIL
(1)
PARAMETER VCC Write Current (Active) VCC Read Current (Active) VCC Standby Current WDT = OFF VCC Standby Current WDT = ON VCC Standby Current WDT = ON Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Output HIGH Voltage Reset Output LOW Voltage
TEST CONDITIONS SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 3.6V VIN = VSS to VCC VOUT = VSS to VCC
MIN
TYP
MAX 5 0.4 1 50 20
UNIT mA mA A A A A A V V V V V V V V
0.1 0.1 -0.5 VCC x 0.7
10 10 VCC x 0.3 VCC + 0.5 0.4 0.4 0.4
VIH(1) VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VOLS
VCC > 3.3V, IOL = 2.1mA 2V < VCC 3.3V, IOL = 1mA VCC 2V, IOL = 0.5mA VCC > 3.3V, IOH = -1.0mA 2V < VCC 3.3V, IOH = -0.4mA VCC 2V, IOH = -0.25mA IOL = 1mA VCC - 0.8 VCC - 0.4 VCC - 0.2
0.4
V
Capacitance TA = +25C, f = 1MHz, VCC = 5V
SYMBOL COUT CIN NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested.
(2)
TEST Output Capacitance (SO, RESET, RESET) Input Capacitance (SCK, SI, CS, WP)
MAX. 8 6
UNIT pF pF
CONDITIONS VOUT = 0V VIN = 0V
(2)
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5V 5V
A.C. Test Conditions
Input pulse levels VCC x 0.1 to VCC x 0.9 10ns VCC x0.5
3.3k
1.64k
OUTPUT RESET/RESET 100pF
Input rise and fall times Input and output timing level
1.64k
30pF
FIGURE 10. EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
AC Electrical Specifications
SYMBOL fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC(4) Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Input Rise Time Input Fall Time CS Deselect Time Write Cycle Time
Serial Input Timing (Over operating conditions unless otherwise specified.)
2.7-5.5V PARAMETER MIN 0 500 250 250 200 200 50 50 100 100 500 10 MAX 2 UNIT MHz ns ns ns ns ns ns ns ns ns ns ms
tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
SO
HIGH IMPEDANCE
FIGURE 11. SERIAL INPUT TIMING
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AC Electrical Specifications
SYMBOL fSCK tDIS tV tHO tRO tFO NOTES: 3. This parameter is periodically sampled and not 100% tested. 4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
(3)
Serial Output Timing(Over operating conditions unless otherwise specified.)
2.7-5.5V PARAMETER MIN 0 MAX 2 250 200 0 100 100 UNIT MHz ns ns ns ns ns
Clock Frequency Output Disable Time Output Valid from Clock Low Output Hold Time Output Rise Time Output Fall Time
(3)
CS tCYC SCK
tWH
tLAG
tV SO MSB OUT MSB-1 OUT
tHO
tWL LSB OUT
tDIS
SI
ADDR LSB IN
TABLE 3. SERIAL OUTPUT TIMING
VTRIP VCC 0 Volts tPURST tPURST tR RESET (X5163)
VTRIP
tF tRPD
RESET (X5165)
TABLE 4. POWER-UP AND POWER-DOWN TIMING
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RESET Output Timing
SYMBOL VTRIP PARAMETER Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A Reset Trip Point Voltage, X5163, X5165 Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A Reset Trip Point Voltage, X5163-2.7, X5165-2.7 VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up Reset Time Out VCC Detect to Reset/Output VCC Fall Time VCC Rise Time Reset Valid VCC 100 100 1 100 MIN 4.5 4.25 2.85 2.55 TYP 4.63 4.38 2.92 2.63 20 200 280 500 MAX 4.75 4.5 3.0 2.7 UNIT V
VTH tPURST tRPD(5) tF(5) tR(5) VRVALID NOTES:
mV ms ns s s V
5. This parameter is periodically sampled and not 100% tested. 6. Typical values not tested.
CS/WDI
tCST RESET
tWDO
tRST
tWDO
tRST
RESET
FIGURE 12. CS/WDI VS. RESET/RESET TIMING
RESET/RESET Output Timing
SYMBOL tWDO PARAMETER Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS Pulse Width to Reset the Watchdog Reset Time Out MIN 100 450 1 400 100 200 300 TYP 200 600 1.4 MAX 300 800 2 UNIT ms ms sec ns ms
tCST tRST
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tTHD VCC VTRIP tTSU tRP tP tVPH
tVPS
CS
tVPS VP
tVPH
tVPO
SCK
VP SI
tVPO
FIGURE 13. VTRIP SET CONDITIONS
tTHD VCC VTRIP tTSU tVPS tP tVP1 tRP
CS
tVPS
tVPH
tVPO
SCK
VCC
VP SI
tVPO
FIGURE 14. VTRIP RESET CONDITIONS
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VTRIP Programming Specifications: VCC = 1.7-5.5V; Temperature = 0C to 70C
PARAMETER tVPS tVPH tP tTSU tTHD tWC tRP tVPO VP VTRAN Vta1 Vta2 Vtr Vtv SCK VTRIP Program Voltage Setup time SCK VTRIP Program Voltage Hold time VTRIP Program Pulse Width VTRIP Level Setup time VTRIP Level Hold (stable) time VTRIP Write Cycle Time VTRIP Program Cycle Recovery Period (Between successive programming cycles) SCK VTRIP Program Voltage Off time before next cycle Programming Voltage VTRIP Programed Voltage Range Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25C.) Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP] (Programmed at 25C.) VTRIP Program Voltage repeatability (Successive program operations.) (Programmed at 25C.) VTRIP Program variation after programming (0-75C). (Programmed at 25C.) 10 0 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25 DESCRIPTION MIN 1 1 1 10 10 10 MAX UNIT s s s s ms ms ms ms V V V mV mV mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
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18 16 14 12 ISB (A) 10 8 6 4 2 0 -40 25 TEMP (C) 90 WATCHDOG TIMER OFF (VCC = 3V, 5V) WATCHDOG TIMER ON (VCC = 5V) RESET (SECONDS) WATCHDOG TIMER ON (VCC = 5V) 1.9 1.8 1.7 1.6 25C 1.5 1.4 1.3 1.2 1.1 1 1.7 2.4 3.1 3.8 4.5 5.2 VOLTAGE 90C -40C
FIGURE 15. VCC SUPPLY CURRENT VS. TEMPERATURE (ISB)
5.025 5.000 4.975 VOLTAGE 3.525 3.500 3.475 2.525 2.500 2.475 0 25 TEMPERATURE 85 VTRIP = 2.5V VTRIP = 3.5V VTRIP = 5V
FIGURE 16. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1)
0.8 0.75 RESET (SECONDS) 0.7 0.65 0.6 0.55 0.5 0.45 1.7 2.4 3.1 3.8 4.5 5.2 VOLTAGE 90C 25C -40C
FIGURE 17. VTRIP vs. Temperature (programmed at 25C)
205 200 195
FIGURE 18. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0)
205 200 195 RESET (SECONDS) 190 185 180 175 170 165 160 90C 25C -40C
190 TIME (MS) 185 180 175 170 165 160 -40 25 DEGREES C 90
1.7
2.4
3.1 VOLTAGE
3.8
4.5
5.2
FIGURE 19. tPURST VS. TEMPERATURE
FIGURE 20. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1)
16
FN8128.1 May 16, 2005
X5163, X5165 Packaging Information
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.050 (1.27) 0.010 (0.25)
0.010 (0.25) 0.020 (0.50)
X 45
0.050" TYPICAL
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
17
FN8128.1 May 16, 2005
X5163, X5165 Packaging Information
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .177 (4.5)
.252 (6.4) BSC
.193 (4.9) .200 (5.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) GAGE PLANE 0 - 8 .019 (.50) .029 (.75) DETAIL A (20X) SEATING PLANE
.031 (.80) .041 (1.05)
SEE DETAIL "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
18
FN8128.1 May 16, 2005
X5163, X5165 Ordering Information
VCC RANGE 4.5-5.5V VTRIP RANGE 4.5.4.75 PACKAGE 8-Pin PDIP OPERATING TEMPERATURE RANGE 0C - 70C -40C - 85C 8L SOIC 0C - 70C -40C - 85C 14L TSSOP 0C - 70C -40C - 85C 4.5-5.5V 4.25.4.5 8-Pin PDIP 0C - 70C -40C - 85C 8L SOIC 0C - 70C 0C - 70C 0C - 70C 0C - 70C -40C - 85C -40C - 85C 14L TSSOP 0C - 70C 0C - 70C -40C - 85C -40C - 85C 2.7-5.5V 2.85-3.0 8-Pin PDIP 0C - 70C -40C - 85C 8L SOIC 0C - 70C 0C - 70C -40C - 85C -40C - 85C 14L TSSOP 0C - 70C -40C - 85C -40C - 85C 2.7-5.5V 2.55-2.7 8-Pin PDIP 0C - 70C -40C - 85C 8L SOIC 0C - 70C 0C - 70C -40C - 85C -40C - 85C 14L TSSOP 0C - 70C 0C - 70C -40C - 85C X5163V14-2.7 X5163V14-2.7T1 X5163V14I-2.7 PART NUMBER RESET (ACTIVE LOW) X5163P-4.5A X5163PI-4.5A X5163S8-4.5A X5163S8I-4.5A X5163V14-4.5A X5163V14I-4.5A X5163P X5163PI X5163S8 X51638S8 X5163S8T1 X5163S8T2 X5163S8I X5163S8IT1 X5163V14 X5163V14T1 X5163V14I X5163V14IT1 X5163P-2.7A X5163PI-2.7A X5163S8-2.7A X5163S8-2.7AT1 X5163S8I-2.7A X5163S8I-2.7AT1 X5163V14-2.7A X5163V14I-2.7A X5163V14I-2.7T1 X5163P-2.7 X5163PI-2.7 X5163S8-2.7 X5163S8-2.7T1 X5163S8I-2.7 X5165V14-2.7A X5165V14I-2.7A X5165V14I-2.7T1 X5165P-2.7 X5165PI-2.7 X5165S8-2.7 X5165S8-2.7T1 X5165S8I-2.7 X5165S8I-2.7T1 X5165V14-2.7 X5165V14-2.7T1 X5165V14I-2.7 X5165S8I-2.7A X5165S8I X5165S8IT1 X5165V14 X5165V14T1 X5165V14I X5165V14IT1 X5165P-2.7A X5165PI-2.7A X5165S8-2.7A X5165S8T1 X5165PI-4.5A X5165S8-4.5A X5165S8I-4.5A X5165V14-4.5A X5165V14I-4.5A X5165P X5165PI X5165S8 PART NUMBER RESET (ACTIVE HIGH)
19
FN8128.1 May 16, 2005
X5163, X5165
Part Mark Information X5163, X51665 W X
Blank = 8-Lead SOIC V = 14 Lead TSSOP Blank = 5V 10%, 0C to +70C, VTRIP = 4.25-4.5 A = 5V10%, 0C to +70C, VTRIP = 4.5-4.75 I = 5V 10%, -40C to +85C, VTRIP = 4.25-4.5 IA = 5V 10%, -40C to +85C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0C to +70C, VTRIP = 2.55-2.7 FA = 2.7V to 5.5V, 0C to +70C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, -40C to +85C, VTRIP = 2.55-2.7 GA = 2.7V to 5.5V, -40C to +85C, VTRIP = 2.85-3.0
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN8128.1 May 16, 2005

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